This thesis provides a new approach to designing smart electronic chips called agent chips. It provides a layered argumentation system for specifying smart systems and an automated method for synthesizing smart electronic chips from an agent specification in the layered argumentation system. The layered argumentation system is a consistent instantiation of a logic based argumentation system extended with Brooks’ subsumption concept, varying degrees of confidence, and fuzzy operators. The layered argumentation system provides a conceptual and behavioral decomposition of smart systems into varying degrees of confidence or competence. Particularly, the thesis provides a new method of compiling the layered argumentation system into hardware description formats, such as RTL-VHDL (Register Transfer Level–VLSI Hardware Description Language) or RTL-Verilog, which is synthesized using computer-assisted tools to develop ASIC (Application Specific Integrated Circuits) masks or FPGA (Field Programmable Gate Arrays) configurations. To prevent abnormal behaviors that can be caused by loops in the theories of layered argumentation system, it provides algorithms for detecting loops and algorithms for removing loops preserving intensional knowledge. Experiments generating digital circuit description from layered argumentation system are reported. Finally, tools for generating general logic programs and hardware description from layered argumentation theories are provided.